Integrated circuits (ICs) are formed on semiconductor wafers. The semiconductor wafers are then sawed into chips. The fabrication of integrated circuits includes many process steps such as deposition, chemical mechanical polish (CMP), plating, and the like. Accordingly, wafers are transported between different fabrication tools for different process steps.
A challenge faced by integrated circuit manufacturing industry is that to improve cost efficiency, wafers become increasingly larger. In the meantime, wafers also have become thinner. Furthermore, in the manufacturing of integrated circuits, wafers may need to be thinned. For example, in the 3DIC technology, wafer thinning is used to thin down wafers to expose through-substrate vias (TSVs) formed therein, where the TSVs are important components for wafer/die stacking. However, handling such thin wafers is not easy. For example, the thin wafers may suffer from breakage, during the transportation and some processes, during which mechanical stress may be applied to the wafers.
To reduce the likelihood of breakage during transportation or a process, thin wafers may need to be strengthened. For example, a thin wafer is strengthened by bonding to a carrier. Therefore, the wafer can be supported mechanically by the carrier. After the process finishes, the wafer is de-bonded from the carrier. Such a temporary carrier has also become an important part to enable 3DIC development because both the front side and the back side of the wafer need to be processed.